View MSM6562B-XX_714442.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor MSM6562B-XX 1/50 general description the MSM6562B-XX controls a character type dot matrix lcd in combination with an 8-bit or 4- bit microcontroller. the MSM6562B-XX can control a display of up to 40 characters. with the display data serial transfer function, the MSM6562B-XX, when used in combination with the character extension ic (msm5259), can control a maximum of 80 characters. features ? easy interface with an 8-bit or 4-bit microcontroller. ? dot matrix lcd controller driver for 5 7 dots font or 5 10 dots font. ? automatic power on reset. ? 16 common signal drivers and 100 segment signal drivers are built in. ? can control up to 80 characters when used in combination with msm5259. ? built-in character generator rom for 160 characters with 5 7 dots font and 32 characters with 5 10 dots font. ? character patterns can be programmed by cg ram. (5 8 dots font: 8 kinds, 5 11 dots font: 4 kinds) ? 1/8 duty (1 line; 5 7 dots + cursor), 1/11 duty (1 line; 5 10 dots + cursor), or 1/16 duty (2 lines; 5 7 dots + cursor) selectable. ? built-in rc oscillation circuit by an external resistor or an internal resistor. ? built-in bias dividing resistors for lcd driving. ? built-in contrast adjusting circuit. ? bidirectional transfer available on segment output. ? aluminum pad chip (product name: MSM6562B-XX) xx indicates code number. ? semiconductor MSM6562B-XX dot matrix lcd controller driver e2b0035-27-y3 this version: nov. 1997 previous version: mar. 1996
? semiconductor MSM6562B-XX 2/50 block diagram l cp df seg 1 - 100 do shl 0 shl 1 100 100 100 16 16 5 5 8 8 7 7 8 8 7 8 5 5 4 4 v dd v ss osc 2 e r/w rs 0 rs 1 db 0 - db 3 db 4 - db 7 t 1 t 2 t 3 timing generation circuit input/ output buffer test circuit lcd bias voltage dividing circuit contrast register (cr) busy flag (bf) instruction register (ir) instruction decoder (id) data register (dr) address counter (adc) 16-bit shift register character generator ram (cg ram) display data ram (dd ram) common signal driver cursor blink control parallel/ serial conversion character generator rom (cg rom) 100-bit shift register 100-bit latch segment signal driver osc r osc 1 v 1 v 2 v 3 ' v 3 v 4 v 5 v 5 ' 8 com 1 - 16
? semiconductor MSM6562B-XX 3/50 input and output configuration n p v dd n p v dd v dd n p v dd v dd v dd p n n p v dd applied to pin e. applied to pins r/w, rs 0 and rs 1 . applied to do, cp, l and df. applied to db 0 - db 7 . v dd applied to pins t 1 , t 2 and t 3 . n p
? semiconductor MSM6562B-XX 4/50 pin descriptions shl 0 shl 1 ll lh hl hh segment data transfer direction seg 1 ? seg 100 seg 100 ? seg 1 seg 1 ? seg 50 t seg 100 ? seg 51 seg 100 ? seg 1 symbol description r/w read/write selection input pin. "h": read, and "l": write register selection input pins. rs 0 "h" rs 1 "h": data register rs 0 "l" rs 1 "h" : instruction register rs 0 "l" rs 1 "l" : contrast register rs 0 , rs 1 e input pin for data input/output between cpu and MSM6562B-XX and for activating instruction. db 0 - db 7 input/output pins for data send/receive between cpu and MSM6562B-XX. osc 1 , osc 2 , osc r clock oscillating pins required for internal operation upon receipt of cpu instruction and the lcd drive signal. when oscillated by an external resistor, connect a resistor between osc 1 and osc 2 . when oscillated by a built-in resistor, connect osc r and osc 2 externally. com 1 - com 16 lcd common signal output pins. seg 1 - seg 100 lcd segment signal output pins. do data output pin to send serial data to the character extension ic. cp clock output pin to transfer the serial data to the character extension ic. l latch output pin to latch the transferred data to the character extension ic. df output pin for the alternating signal (df, display frequency) required for an lcd display. v dd power supply pin. v ss ground pin. v 1 - v 5 , v 3 ' bias voltage input pins to drive an lcd and bias setting pin. (built-in bias dividing resistor) 1/4 bias : connect v 2 and v 3 . leave v 3 ' open. 1/5 bias : connect v 3 and v 3 '. since v lcd value depends on v 5 voltage, connect a variable resistor between v 5 pin and v ss potential or connect v 5 pin and v 5 ' pin to adjust v lcd . v 5 ' contrast adjusting voltage output pin. shl 0 , shl 1 input pins to control the transfer direction of the segment signal output data. see table below.
? semiconductor MSM6562B-XX 5/50 absolute maximum ratings recommended operating conditions storage temperature junction temperature input voltage parameter supply voltage symbol v dd v 1 , v 2 , v 3 , v 4 , v 5 v i supply voltage for lcd display condition ta = 25c ta = 25c ta = 25c t j t stg rating C0.3 to + 7.0 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 150 C55 to + 150 unit v v v c c applicable pin v dd , v ss r / w, rs 1 , rs 0 , e, db 0 - db 7 osc 1 v 1 , v 2 , v 3 , v 4 , v 5 operating temperature lcd driving voltage parameter supply voltage symbol v dd v lcd condition v dd C v ss 1/4 bias * 1 t op range 4.5 to 5.5 3.0 to 5.5 * 3 C30 to +85 unit v v c applicable pin v dd , v ss v v dd , v 5 3.0 to 5.5 * 3 v dd C v ss 1/5 bias * 2 *1 this voltage should be applied to v dd C v 5 . voltages applicable to v 1 , v 2 , v 3 and v 4 are as follows: v 1 = v dd C 1/4 (v dd C v 5 ) v 2 = v 3 = v dd C 1/2 (v dd C v 5 ) v 4 = v dd C 3/4 (v dd C v 5 ) *2 this voltage should be applied to v dd C v 5 . voltages applicable to v 1 , v 2 , v 3 and v 4 are as follows: v 1 = v dd C 1/5 (v dd C v 5 ) v 2 = v dd C 2/5 (v dd C v 5 ) v 3 = v dd C 3/5 (v dd C v 5 ) v 4 = v dd C 4/5 (v dd C v 5 ) *3 the relation of v dd > v 1 > v 2 3 v 3 (=v 3 ') > v 4 > v 5 3 v ss must be kept. (high ?? low) lcd driving voltage can be adjusted by varying v 5 . however, v 5 cannot be used under v ss voltage.
? semiconductor MSM6562B-XX 6/50 electrical characteristics dc characteristics parameter "h" input voltage symbol v ih1 condition unit v applied pin r/w, rs 0 , rs 1 , e, db 0 - db 7 min. 2.2 typ. max. v dd v "l" input voltage v il1 C0.3 0.6 "h" input voltage "l" input voltage "h" output voltage "l" output voltage "h" output voltage "l" output voltage com voltage drop seg voltage drop input leakage current "h" input current v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v c v s i il i ih2 i o = C0.205ma i o = 1.6ma i o = C40 m a i o = 40 m a i o = 40 m a (note 1) v i = v dd v i = v ss i o = 40 m a (note 1) v dd C 0.8 C0.3 2.4 0.9v dd C34 C83 v dd 0.8 0.4 0.1v dd 2.3 3.0 1 C1 C204 v v v v v v v v m a m a m a osc 1 shl 0 , shl 1 db 0 - db 7 do, cp, l, df, osc 2 seg 1 - seg 100 e, shl 0 , shl 1 r/w, rs 0 , rs 1 , db 0 - db 7 com 1 - com 16 v i = v dd except the current flowing to the pull-up resistor and output driving mos. v dd = 5.0v v i = v ss (v dd = 4.5 to 5.5v, ta = -30 to +85c) 2 m a "l" input current i il2 v dd = 5.0v e = "l" level, shl 0 , shl 1 = "l" level built-in r f oscillation or external clock input to osc 1 . external clock frequency (f in ) is 270khz. r/w, rs 0 , rs 1 , and db 0 to db 7 are open. output pins are all no load. except bias current for lcd driving. (note 2, 3, 4) supply current i dd ma v dd 1 lcd driving bias resistance lbr k w v dd C v 1 , v 1 C v 2 v 2 C v 3 ', v 3 C v 4 v 4 C v 5 248 v dd , v 1 , v 2 , v 3 , v 3 ' , v 4 , v 5 lcd driving bias voltage (external input) v lcd1 v 3.0 5.5 v dd C v 5 (note 5) 1/5 bias 3.0 5.5 1/4 bias v lcd2 variable range by built-in variable resistor for lcd driving voltage v lcd max v 4.6 v dd = 5.0v, 1/5 bias v lcd min v dd = 5.0v, 1/5 bias 3.7 v dd C v 5 (v 5 ')
? semiconductor MSM6562B-XX 7/50 (note 1) applies to the voltage drop (v c ) from v dd , v 1 , v 4 and v 5 to each common pin (com 1 to com 16 ) as well as to voltage drop (v s ) from v dd , v 2 , v 3 and v 5 to each seg pin (seg 1 to seg 100 ) when 40 m a is flowed through one com or seg pin. when output level is at v dd , v 1 , or v 2 level, 40 m a is flowed out, while 40 m a is flowed in when the output level is at v 3 , v 4 or v 5 level. this occurs when 5v is input to v dd , v 1 and v 2 , and 0v is input to v 3 , v 4 and v 5 . (note 2) applies to the current value flowed in the pin v dd , in the case of v dd = 5v, v ss = 0v, v 1 , v 2 = 5v, v 3 , v 4 , v 5 = 0v and v 5 ' is open. (note 3) built-in r f oscillation circuit minimum wiring is required between osc r and osc 2 . leave osc 1 open. (note 4) external clock input circuit leave osc r and osc 2 open. osc 1 osc r osc 2 osc 1 osc r osc 2 (note 5) input the voltage to v 5 . (however, v 5 cannot be used under v ss voltage.) pin n (number of lcd lines) v 1 v 2 v 3 v 4 v 5 v dd C v lcd v dd C v lcd v dd C v lcd v dd C 3v lcd v dd C v lcd v dd C v lcd v dd C 2v lcd v dd C 3v lcd v dd C 4v lcd v dd C v lcd 1-line mode bias : 1/4 2-line mode bias : 1/5 2 2 4 4 5 5 5 5 at 1/4 bias : connect v 2 and v 3 externally and leave v 3 ' open. at 1/5 bias : connect v 3 and v 3 ' externally. v lcd is the lcd driving voltage. (for n [number of lcd lines], refer to the explanation of the function setting instruction of the instruction code.) input pulse
? semiconductor MSM6562B-XX 8/50 ac characteristics parameter symbol condition unit applicable pin min. typ. max. osc 1 osc 2 r f clock oscillation frequency f osc1 khz 175 270 350 r f = 120 k w 2% (note 1) osc 1 external clock frequency f in khz 125 480 osc r and osc 2 are open. input a pulse to osc 1 . osc 1 external clock duty f duty % 45 50 55 (note 2) osc 1 external clock fall time t ff m s 0.2 (note 3) osc 1 osc r osc 2 built-in r f clock oscillation frequency f osc2 khz 140 280 480 osc 1 is open. connect osc r and osc 2 . osc 1 external clock rise time t rf m s 0.2 (note 3) (note 5) (note 4) (note 1) r f = 120k w 2% minimum wiring is required between osc 1 and r f and between osc 2 and r f . leave osc r open. osc 1 r f osc r osc 2 applies to the pulse to be input to osc 1 v dd t hw t lw f dut y = t hw /(t hw + t lw ) 100 (%) f in waveform 2 v dd 2 v dd 2 (note 2) v dd C 0.8v 0.8v applies to the pulse to be input to osc 1 v dd C 0.8v 0.8v t rf t ff f in waveform (note 3) applies to the pulse to be input to osc 1 . (note 4) see note 4 to "dc characteristics." (note 5) see note 3 to "dc characteristics."
? semiconductor MSM6562B-XX 9/50 switching characteristics 1. timing for input from the cpu (write operation) parameter symbol t b t w t a t r t f t l t c t i t h 40 220 10 210 500 100 10 20 20 ns ns ns ns ns ns ns ns ns min. typ. max. unit r/w, rs 0 and rs 1 setup time e "h" pulse width r/w, rs 0 and rs 1 hold time e rise time e fall time e "l" pulse width e cycle time db 0 to db 7 input data setup time db 0 to db 7 input data hold time (v dd = 4.5 to 5.5v, ta = C30 to +85c) input data v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 t c t h t i t a t w v il1 v il1 v il1 t b t f t r t l v il1 v ih1 v il1 v ih1 rs 1 , 0 r/w e db 0-7
? semiconductor MSM6562B-XX 10/50 parameter symbol t b t w t a t r t f t l t c t d t o 40 220 10 210 500 20 20 20 150 ns ns ns ns ns ns ns ns ns min. typ. max. unit r/w, rs 0 and rs 1 setup time e "h" pulse width r/w, rs 0 and rs 1 hold time e rise time e fall time e "l" pulse width e cycle time db 0 to db 7 data ouput delay time db 0 to db 7 data ouput hold time (v dd = 4.5 to 5.5v, ta = C30 to +85c) v ih1 v il1 v ih1 v il1 v oh1 v ol1 v oh1 v ol1 t c t o t d t a t w v il1 v il1 v il1 t b t f t r t l v il1 v ih1 v il1 v il1 rs 1 , 0 r/w e db 0-7 output data 2. timing for output to the cpu (read operation)
? semiconductor MSM6562B-XX 11/50 parameter symbol t hw1 t lw t s t dh t su t ho t hw2 t m 800 800 300 300 500 100 800 C1000 1000 ns ns ns ns ns ns ns ns min. typ. max. unit cp "h" pulse width cp "l" pulse width do setup time do hold time l clock setup time l clock hold time l "h" pulse width df delay time (v dd = 4.5 to 5.5v, ta = C30 to +85c) v oh2 v oh2 v oh2 v ol2 t s v oh2 v oh2 v ol2 v ol2 v oh2 v ol2 v oh2 t dh t su t ho v oh2 v oh2 v ol2 t hw2 v oh2 t m t hw1 t lw do cp l df 3. timing for output to character extension ic
? semiconductor MSM6562B-XX 12/50 functional description 1. instruction register (ir), data register (dr), contrast register (cr) these three registers are selected by the register selector pins, rs 0 and rs 1 . when rs 0 and rs 1 are "h" level input, the dr is selected and when rs 0 = "l" level input and rs 1 = "h", the ir is selected. on the other hand, when rs 0 and rs 1 are "l" level input, the cr is selected. (when rs 0 = "h" level input and rs 1 = "l", the registers are ignored.) the ir is used to store the address codes for the display data ram (dd ram) or character generator ram (cg ram) and instruction codes. the ir can be written into, but not be read out by the microcomputer (cpu). the cr can be used to read out and write. the cr values provide 0 to 1f (hexadecimal) and when this value is 0, v lcd is lowest. on the other hand, when it is 1f, it is highest. (the initial value is 1f.) therefore, the contrast can be adjusted by varying the cr value (providing that v 5 and v 5 ' are connected). the dr is used to write into/read out the data to/from the dd ram or cg ram. the data written to the dr by the cpu is automatically written to the dd ram or cg ram as an internal operation. when an address code is written to the ir, the data (of the specified address) is automatically transferred from the dd ram or cg ram to the dr. by having the cpu subsequently read the dr (from the dr data), it is possible to verify the dd ram or cg ram data. after the writing of the dr by the cpu, the dd ram or cg ram of the next address is selected to be ready for the next cpu writing. likewise, after the reading out of the dr by the cpu, the dd ram or cg ram data is read out by the dr to be ready for the next cpu reading. write/read to and from the three registers is carried out by the read/write (r/w) pin. r/w rs 0 rs 1 llh hlh lhh hhh lll hll function ir write read of busy flag (bf) and address counter (adc) dr write dr read cr write cr read 2. busy flag (bf) when the busy flag output is at "h", it indicates that the MSM6562B-XX is engaged in internal operation. when the busy flag is at "h" level, any new instruction is ignored. when r/w = "h", rs 0 = "l", and rs 1 = "h", the busy flag is output from db 7 . new instruction should be input when bf is "l" level. when the busy flag is set to "h", the output code of the address counter (adc) are undefined. table 1 register and r/w pins function table
? semiconductor MSM6562B-XX 13/50 3. address counter (adc) the address counter (adc) allocates the address for the dd ram and cg ram and also for the cursor display. when the instruction code for the dd ram address or cg ram address setting is input to the ir, after deciding whether it is the dd ram or cg ram, the address code is transferred from the ir to the adc. after writing (reading) the display data to (from) the dd ram or cg ram, the adc is automatically incremented (decremented) by 1 as its internal operation. the data of the adc is output to db 0 - db 6 under the conditions that r/w = "h", rs 0 = "l", rs 1 = "h" and bf = "l". 4. timing generator circuit this circuit generates timing signals used for internal operations upon receipt of cpu instruc- tion. it also generates timing signals for activating such internal circuits as the dd ram, cg ram and cg rom. it is so designed that the internal operation caused by accessing from the cpu will not interfere with the internal operation caused by the lcd display. consequently, when data is written from the cpu to dd ram no ill effect, e.g., flickering occurs in portions other than the display where the data is written. in addition, the circuit generates transfer signals to the character extension ic (msm5259).
? semiconductor MSM6562B-XX 14/50 5. display data ram (dd ram) this ram is used to store the display data of 8-bit character codes (see table 2). dd ram address corresponds to the display position of the lcd. the correspondence between the two is described in the following. msb lsb db 6 db 0 ll h l h l h a 2 hexadecimal notation hexadecimal notation adc (example) when dd ram address is 2a dd ram address (set to adc) is expressed in hexadecimal notation as shown below: 1-1) correspondence between address and display position in the 1-line display mode 00 01 02 03 04 4e 4f 79 80 first digit 2345 msb lsb display position dd ram address (hex.) 00 01 02 03 12 13 19 20 first digit 2 3 4 4f 00 01 02 11 12 19 20 first digit 2 3 4 01 02 03 04 13 14 19 20 first digit 2 3 4 (display shifted to right) (display shifted to left) 1-2) when the MSM6562B-XX alone is used, up to 20 characters can be displayed from the first digit to the twentieth digit. when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below:
? semiconductor MSM6562B-XX 15/50 1-3) when the MSM6562B-XX is used with one msm5259, up to 28 characters can be displayed from the first digit to the twenty-eighth digit as shown below: 00 01 02 03 12 13 19 20 first digit 2 3 4 14 21 15 22 16 23 17 24 18 25 19 26 1a 27 1b 28 msm5259 display MSM6562B-XX display 4f 00 01 02 11 12 13 14 15 16 17 18 19 1a 19 20 first digit 2 3 4 21 22 23 24 25 26 27 28 msm5259 display MSM6562B-XX display 01 02 03 04 13 14 15 16 17 18 19 1a 1b 1c (display shifted to right) (display shifted to left) 00 01 02 03 12 13 19 20 first digit 2 3 4 14 21 15 22 16 23 17 24 18 25 19 26 1a 27 1b 28 msm5259 (1) display MSM6562B-XX display 1c 1d 4c 4d 4e 4f 29 30 77 78 79 80 msm5259 (2)-(7) display msm5259 (8) display (only the half of the segment output pins, i.e., o 1 to o 20 , are used.) when the display is shifted by instruction, the correspondence between the lcd display and dd ram address changes as shown below: 1-4) since the MSM6562B-XX has a dd ram with a capacity of 80 characters, up to 8 devices of msm5259 can be connected to MSM6562B-XX so that 80 characters can be displayed.
? semiconductor MSM6562B-XX 16/50 2-1) correspondence between address and display position in the 2-line display mode (note) note that the last address of the first line and the leading address of the second line are not consecutive. 2-2) when the MSM6562B-XX alone is used, up to 40 characters (20 character 2 lines) can be displayed from the first digit to the twentieth digit. when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below: 2-3) when the MSM6562B-XX is used with one msm5259, up to 56 characters (28 characters 2 lines) can be displayed from the first digit to the twenty-eighth digit as shown below: 00 01 02 03 04 26 27 39 40 first digit 2345 display position dd ram address (hex.) 40 41 42 43 44 66 67 first line second line 00 01 02 03 12 13 19 20 first digit 2 3 4 40 41 42 43 52 53 first line second line first line second line 27 00 01 02 11 12 19 20 first digit 2 3 4 67 40 41 42 51 52 01 02 03 04 13 14 19 20 first digit 2 3 4 41 42 43 44 53 54 first line second line (display shifted to right) (display shifted to left) 00 01 02 03 12 13 19 20 first digit 2 3 4 40 41 42 43 52 53 first line second line 14 21 54 15 22 55 16 23 56 17 24 57 18 25 58 19 26 59 1a 27 5a 1b 28 5b msm5259 display MSM6562B-XX display
? semiconductor MSM6562B-XX 17/50 when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below: 27 00 01 02 11 12 19 20 first digit 2 3 4 67 40 41 42 51 52 first line second line 13 21 53 14 22 54 15 23 55 16 24 56 17 25 57 18 26 58 19 27 59 1a 28 5a msm5259 display MSM6562B-XX display (display shifted to right) 01 02 03 04 13 14 19 20 first digit 2 3 4 41 42 43 44 53 54 first line second line 15 21 55 16 22 56 17 23 57 18 24 58 19 25 59 1a 26 5a 1b 27 5b 1c 28 5c msm5259 display MSM6562B-XX display (display shifted to left) (only the half of the segment output pins, i.e., o 1 to o 20 , are used.) 00 01 02 03 12 13 19 20 first digit 234 14 21 15 22 16 23 17 24 18 25 19 26 1a 27 1b 28 msm5259 (1) display msm6562b display 1c 1d 24 25 26 27 29 30 37 38 39 40 msm5259 (2) display msm5259 (3) display 40 41 42 43 52 53 54 55 56 57 58 59 5a 5b 5c 5d 64 65 66 67 2-4) since the MSM6562B-XX has a dd ram with a capacity of 80 characters, up to 3 devices of msm5259 can be connected to the MSM6562B-XX in the 2-line display mode. 6. character generator rom (cg rom) the cg rom is used to generate 5 7 dot (160 kinds) character patterns or 5 10 dot (32 kinds) character patterns from an 8-bit dd ram character code signal. the correspondence of 8-bit character codes to character patterns is shown in table 2. when the 8-bit character code of the cg rom is written to the dd ram, the character pattern of the cg rom corresponding to the code is displayed on the lcd display position correspond- ing to the dd ram address.
? semiconductor MSM6562B-XX 18/50 table 2 character codes and character patterns of standard code (msm6562b-01) lower 4 bits upper 4 bits 0000 lsb 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0001 cg ram (1) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (9) (7) (8) (2) # $ % & ( ) * + C . / ! 2 3 4 5 6 7 8 9 : ; < = > ? 1 0 b c d e f g h i j k l m n o a @ r s t u v w x y z [ ] ^ _ q p b c d e f n h i j k l m n o a / r s t u v w x y z { ? } ? ? q p b e m s r g C1 j x n ? ? a q w s p x q r ?
? semiconductor MSM6562B-XX 19/50 7. character generator ram (cg ram) the cg ram is used to display user's original character patterns other than those stored in the cg rom. the cg ram has the capacity (64 bytes = 512 bits) to write 8 kinds for 5 7 dots or 4 kinds for 5 10 dots. when displaying character patterns stored in the cg ram, write 8-bit character codes (00 to 07 or 08 to 0f; hex.) shown on the left in table 2 to the dd ram. it is then possible to output the character pattern to the lcd display position corresponding to the dd ram address. the following is a description on how to write and read character patterns to and from the cg ram. (1) when the character pattern is 5 7 dots (see table 3) ? method of writing character pattern into the cg ram by the cpu : the cg ram address bits 0 to 2 correspond to the line position of the character pattern. first, set increment or decrement by the cpu, and then input the cg ram address. after this, write character pattern into the cg ram through db 0 to db 7 line by line. db 0 to db 7 correspond to the cg ram data bits 0 to 7 in table 3. the display of the character pattern is turned on when "h" is set as input data, while it is turned off when "l" is set as the input data. since the adc is automatically incremented or decremented by 1 after writing the data to the cg ram, it is not necessary to set the cg ram address again. when performing a cursor indication, set to "0" all the input data for the line the cg ram address bits 0 to 2 of which are all "1". although the cg ram data bits 0 ~ 4 are output to the lcd as display data, the cg ram data bits 5 ~ 7 are not. it is possible, however, to use the cg ram as a data ram. ? method of displaying the cg ram character pattern to the lcd : the cg ram is selected when high-order 4 bits of the character code are all "l". since bit 3 of the character code is invalid, the display of "0" in table 3 is selected by character code "00" or "08" (hex.). when the 8-bit character code of the cg ram is written to the dd ram, the character pattern of the cg ram is displayed on the lcd display position corresponding to the dd ram address. (dd ram data bits 0 to 2 correspond to cg ram address bits 3 to 5.)
? semiconductor MSM6562B-XX 20/50 (2) when the character pattern is 5 10 dots (see table 4). ? method of writing character pattern into the cg ram by the cpu : the cg ram address bits 0 to 3 correspond to the line position of the character pattern. first, set increment or decrement by the cpu, and then input the cg ram address. after this, write the character pattern into the cg ram through db 0 to db 7 line by line. db 0 to db 7 correspond to the cg ram data bits 0 to 7, in table 4. the display of the character pattern is turned on when "h" is set as the input data, while it is turned off when "l" is set as the input data. since the adc is automatically incremented or decremented by 1 after writing the data to the cg ram, it is not necessary to set the cg ram address again. when performing a cursor indication, set to "0" all the input data for the line the cg ram address bits 0 to 2 are all "1". cg ram data is displayed on the lcd when the cg ram data ranges from cg ram data bits 0 to 4 and the cg ram addresses (address bits 0 to 3) are "0" to "a" (hex.). other cg ram data is not displayed on the lcd (that is, when the cg ram data ranges from cg ram data bits 5 to 7 and the cg ram addresses (address bits 0 to 3) are "b" to "f" (hex.)). it is possible, however, to read such cg ram data through db 0 to db 7 . ? method of displaying the cg ram character pattern to the lcd : the cg ram is selected when high-order 4 bits of the character code are all "l". since bits 0 and 3 of the character code are invalid, the display of " b " in table 4 is selected by character codes "00", "01", "08" and "09" (hex.). when the 8-bit character code of the cg ram character code is written to the dd ram,the character pattern of the cg ram is displayed on the lcd display position corresponding to the dd ram address. (dd ram data bits 1 to 2 correspond to cg ram address bits 4 to 5.)
? semiconductor MSM6562B-XX 21/50 table 3 example of the cg ram data (character pattern) corresponding to the cg ram addresses when the character pattern is 5 7 dots, and relationship between character patterns and the dd ram data 000000 001 010 011 100 101 110 111 xxx 011 100 100 100 100 100 011 000 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 cg ram address cg ram data (character pattern) msb lsb msb lsb 543210 765 43210 000 0x000 dd ram data (character code) msb lsb 65 43210 7 001000 001 010 011 100 101 110 111 xxx 100 100 101 110 101 100 100 000 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 000 0x001 111000 001 010 011 100 101 110 111 xxx 011 001 001 001 001 001 011 000 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 000 0x111 ? x : don't care
? semiconductor MSM6562B-XX 22/50 table 4 example of the cg ram data (character pattern) corresponding to the cg ram addresses when the character pattern is 5 10 dots, and relationship between character patterns and the dd ram data cg ram address cg ram data (character pattern) msb lsb msb lsb 543210 765 43210 00 0 0 x 0 0 x dd ram data (character code) msb lsb 65 43210 7 xxx 000 000 011 100 111 100 111 100 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 0 100 100 000 xxx 0 0 0 x 0 0 0 x 000000 001 010 011 100 101 110 111 000 001 010 011 0 0 0 0 0 0 0 1 1 1 1 100 101 110 111 1 1 1 1 00 0 0 x 0 1 x xxx 000 000 011 100 100 100 011 000 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 000 011 000 xxx 0 1 0 x 1 0 0 x 000000 001 010 011 100 101 110 111 000 001 010 011 0 0 0 0 0 0 0 1 1 1 1 100 101 110 111 1 1 1 1 00 0 0 x 1 1 x xxx 000 000 110 010 100 100 011 000 0 0 1 1 0 0 1 0 0 0 1 0 1 1 0 0 000 000 000 xxx 0 0 0 x 0 0 0 x 000000 001 010 011 100 101 110 111 000 001 010 011 0 0 0 0 0 0 0 1 1 1 1 100 101 110 111 1 1 1 1 x : don't care
? semiconductor MSM6562B-XX 23/50 8. cursor and blink control circuit this circuit generates the lcd cursor and blink. this circuit is under the control of the cpu program. the display of the cursor or blink on the lcd is made at a position corresponding to the dd ram address set to the adc. the figure below shows an example of the cursor and blink position when the value of the adc is set at "07" (hex.). (note) the cursor and blink are displayed even when the cg ram address is set to the adc. for this reason, it is necessary to inhibit the display of the cursor and blink while the cg ram address is set to the adc. first line second line lll adc 0 l h hh db 0 db 6 7 00 01 02 03 04 05 56 first digit 2 3 4 in 1-line display mode 06 7 07 8 08 9 4e 79 4f 80 00 01 02 03 04 05 56 first digit 2 3 4 06 7 07 8 08 9 26 39 27 40 40 41 42 43 44 45 46 47 48 66 67 in 2-line display mode cursor and blink position cursor and blink position
? semiconductor MSM6562B-XX 24/50 9. lcd display circuit (com 1 to com 16 , seg 1 to seg 100 , l, cp, do, df, shl 0 , shl 1 ) : since the MSM6562B-XX provides the com signal outputs (16 outputs) and the seg signal outputs (100 outputs), even a single MSM6562B-XX device can display 20 characters (1-line display) or 40 characters (2-line display). the character pattern data is converted into the serial data and is serially transferred through the shift register. the transfer direction of the serial data is controlled by shl 0 and shl 1 and is shown as follows. shl 0 shl 1 ll lh hl hh transfer direction seg 1 ? seg 100 seg 100 ? seg 1 seg 1 ? seg 50 t seg 100 ? seg 51 seg 100 ? seg 1 connect shl 0 and shl 1 to v dd or v ss . keep the set states of the shl 0 and shl 1 pins unchanged during ic operation. the seg 1 to seg 100 are used to display 20-digit display on the lcd. to display more than 20 digits, the character extension ic (msm5259) is used. the character extension ic (msm5259) is an extended ic for segment signal output. interfacing with the msm5259 is provided through data output pin (do), clock output pin (cp), latch output pin (l), and display frequency pin (df). the character pattern data is serially transferred to the msm5259 through do and cp. when 60-character (= 1-line display) or 20-character (= 2-line display) is output, the latch pulse is also output through pin l. by this latch pulse, the data transferred serially to the msm5259 is latched to be used as the display data. the display frequency (df) signal required when the lcd is displayed is also output from df pin in synchronization with this latch pulse.
? semiconductor MSM6562B-XX 25/50 10. built-in reset circuit the MSM6562B-XX is automatically initialized when the power is turned on. during initialization, the busy flag (bf) holds "h" and does not accept instructions (other than the busy flag read). the busy flag goes to "h" for 15 ms after v dd reaches 4.5v or more. during initialization, the MSM6562B-XX executes the following instructions : ? display clear ? data length of interface with cpu : 8 bits (8b/4b = "h") ? lcd : 1-line display (n = "l") ? character font : 5 7 dots (f = "l") ? adc : increment (i/d = "h") ? no display shift (s = "l") ? display : off (d = "l") ? cursor : off (c = "l") ? no blink (b = "l") ? contrast data : 1f (hex.) set when the built-in reset circuit is used, the power supply conditions shown in the figure below must be satisfied. if they are not satisfied, because in that case the built-in reset circuit does not operate normally, initialize the MSM6562B-XX by instruction through the cpu (see the section on instruction initialization). if a battery is used as supply voltage source, be sure to initialize the instruction. t off t on v dd 0.2v 4.5v 0.2v 0.2v 0.1ms t on 100ms 1ms t off power on/off waveform
? semiconductor MSM6562B-XX 26/50 11. data bus with cpu the MSM6562B-XX has either a one-step access in 8 bits or a two-step access in 4 bits to execute an instruction so that the MSM6562B-XX can interface with both an 8-bit cpu and a 4-bit cpu. (1) when the interface data length is 8 bits data buses db 0 to db 7 (8 lines) are all used and data input/output is carried out in one step. (2) when the interface data length is 4 bits the 8-bit data input/output is carried out in two steps by using only high-order 4 bits of data buses db 4 to db 7 (4 lines). the first time data input/output is made for high-order 4 bits (db 4 to db 7 when the interfaces data length is 8 bits) and the second time data input/output is made for low- order 4 bits (db 0 to db 3 when the interface data length is 8 bits). even when the data input/output can be completely made through high-order 4 bits, be sure to make another input/output of low-order 4 bits. (example : busy flag read) since the data input/output is carried out in two steps but as one execution, no normal data transfer is executed from the next input/output if accessed only once.
? semiconductor MSM6562B-XX 27/50 ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir0 adc6 adc5 adc4 adc3 adc2 adc1 adc0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 rs 0 r/w e busy (internal operation) db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 instruction register (ir) write busy flag (bf) and address counter (adc) read data register (dr) write busy no busy example of 8-bit data transfer rs 1
? semiconductor MSM6562B-XX 28/50 dr3 rs 0 r/w e db 7 db 6 db 5 db 4 busy flag (bf) and address counter (adc) read busy no busy dr2 dr1 dr0 dr7 dr6 dr5 dr4 adc3 adc2 adc1 adc0 adc6 adc5 adc4 ir3 ir2 ir1 ir0 ir7 ir6 ir5 ir4 busy (internal operation) instruction register (ir) write data register (dr) write example of 4-bit data transfer rs 1
? semiconductor MSM6562B-XX 29/50 12. instruction code ? instruction code table code instruction display clear rs1 rs0r/wdb7 db6 db5 db4 db3 db2 db1 db0 10000000001 description execution time ? cp =? osc =250khz after all display are cleared, address counter for dd ram is set to "00". 1000000001 ] cursor home address counter for dd ram is set to "00". the shifted display returns to the position before shift. the contents of the dd ram are not changed. 1.64ms 1.64ms 100000001i/ds entry mode setting direction of the cursor move and whether display is shifted are set. upon data write or read, the cursor and the display will actually be moved and shifted. 40 m s function setting 100001 8b/ 4b nf ]] the interface data length (8b/4b), the display line numbers (n) and the character font (f) are set. 40 m s cursor/display shift 1000001s/cr/l ]] the cursor and display are shifted without changing the contents of the dd ram. 40 m s display on/off control 10000001dcb the on/off of all display (d), the on/off of the cursor (c) and the blink (b) of the character at the cursor position are set. 40 m s cg ram address setting 10001 acg the address of the cg ram is set and then the cg ram data is specified for the data for transmission and reception. 40 m s the busy flag (bf) indicating that the internal circuits are operating and the contents of address counter are read out. dd ram address setting 1001 add 40 m s busy flag/address read 1 0 1 bf adc 1 m s data is written into the dd ram or cg ram 1 1 0 write data data is read out from the dd ram or cg ram. 1 1 1 read data the data for contrast adjustment is written. 0000 write contrast data the data for contrast adjustment is read. contrast adjusting data read 0010 0 0 1 0 contrast adjusting data write cg ram/dd ram data read cg ram/dd ram data write 40 m s 40 m s 40 m s 40 m s the address of the dd ram is set and then the dd ram data is specified for the data for transmission and reception. read contrast data i/d=1 s=1 s/c=1 r/l=1 8b/4b=1 n=1 f=1 bf=1 : : : : : : : : increment always involves display shift shift of display shift to the right 8 bits 2 lines 5 10-dots engaged in internal operation , i/d=0 , s/c=0 , r/l=0 , 8b/4b=0 , n=0 , f=0 , bf=0 : : : : : : : decrement shift of cursor shift to the left 4 bits 1 line 5 7-dots instruction acceptable dd ram cg ram acg add adc : : : : : display data ram character generator ram cg ram address dd ram address, corresponding to the cursor address address counter, used for both dd ram and cg ram when the frequency is changed, the execution time is also changed. (example) when ? cp or ? osc =270khz, 40s 270 = 37s 250 ] : don't care
? semiconductor MSM6562B-XX 30/50 (1) display clear when this instruction is executed, the lcd display is cleared. the i/d value for the entry mode set instruction is set to 1 (increment). the s value for the entry mode set instruction does not change. when the cursor and blink are being displayed, the blinking and cursor position moves to the left end of the lcd (the left end of the first line in the 2-line display mode). (note) the address counter (adc) goes to "00" (hex.) of the dd ram address. the execution time when the osc oscillation frequency is 250khz is 1.64ms (max.). 13. description of instructions the instruction code is defined as the signal through which the MSM6562B-XX is accessed by the cpu. the MSM6562B-XX begins operation upon receipt of the instruction code input. as the internal processing operation of MSM6562B-XX is started with a timing that does not affect the lcd display, the busy status continues longer than the cpu cycle time. under the busy status (when the busy flag is set to "h"), the MSM6562B-XX does not execute any instructions other than the busy flag read. therefore, it must be confirmed before an instruction code is input from the cpu that the busy flag is set to "l". (2) cursor home when this instruction is executed, the cursor and blinking position move to the left end of the lcd (to the left end of the first line in the 2-line display mode) when the cursor and blink are being displayed. when the display is in shift, the display returns to its original position before shifting. (note) all dd ram data goes to "20" (hex.), while the address counter (adc) goes to "00" (hex.) of the dd ram address. the execution time when the osc oscillation frequency is 250khz is 1.64ms (max.). 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 1 db 0 instruction code 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 1 db 1 x db 0 instruction code x : don't care
? semiconductor MSM6562B-XX 31/50 (3) entry mode set 1 when the i/d is set, the 8-bit character code is written or read to and from the dd ram, the cursor and blink shift to the right by 1 character position (i/d = "h"; increment) or to the left by 1 character position (i/d = "l"; decrement). the address counter (adc) is incremented (i/d = "h") or decremented (i/d = "l") by 1 at this time. even after the character pattern code is written or read to and from the cg ram, the address counter (adc) is incremented (i/d = "h") or decremented (i/ d = "l") by 1. 2 the cursor goes off when c = "l" and it is displayed when d = "h" and c = "h". 2 when s = "h" is set, the character code is written to the dd ram, and then the cursor and blink stop and the entire display shifts to the left (i/d = "h") or to the right (i/d = "l") by 1 character position. when the character is read from the dd ram when s = "h" is set, or when the character pattern data is written or read to or from the cg ram when s = "h" is set, the entire display does not shift, but normal write/read is performed (the entire display does not shift, but the cursor and blink shift to the right (i/d = "h") or to the left (i/d = "l") by 1 character position). when s = "l" is set, the display does not shift, but normal write/read is performed. the execution time, when the osc oscillation frequency is 250khz, is 40 m s. (4) display on/off control 1 the d bit controls whether the character pattern is displayed or not. when d is "h", this bit makes the character pattern display on the lcd. when d is "l", this bit makes the display of the character pattern turned off. the cursor and blink are also cancelled at this time. (note) different from the display clear, the dd ram data is absolutely not rewritten. 3 a blink is cancelled when b = "l" and a blink is executed when d = "h" and b = "h". in the blink mode, all dots (including the cursor) and displaying character pattern (including the cursor) are displayed alternately at 409.6ms (in 5 7 dots character font) or 563.2ms (in 5 10 dots character font) when the osc oscillation frequency is 250khz. the execution time, when the osc oscillation frequency is 250khz, is 40 m s. 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 1 db 2 i/d db 1 s db 0 instruction code 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 0 db 5 0 db 4 1 db 3 d db 2 c db 1 b db 0 instruction code
? semiconductor MSM6562B-XX 32/50 (5) cursor/display shift when s/c = "l" and r/l = "l", the cursor and blink position are shifted to the left by 1 character position (the adc is then decremented by 1). when s/c = "l" and r/l = "h", the cursor and blink position are shifted to the right by 1 character position (the adc is then incremented by 1). when s/c = "h" and r/l = "l", the entire display is shifted to the left by 1 character position. the cursor and blink position are also shifted together with the display (adc remains unchanged). when s/c = "h" and r/l = "h", the entire display is shifted to the right by 1 character position. the cursor and blink position are also shifted together with the display (adc remains unchanged). in the 2-line display mode, the cursor and blink position are shifted from the first line to the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.) in the first line. no such shifting is made in other cases. when shifting the entire display, the display pattern, cursor and blink position are not shifted between lines (from the first line to the second line or vice versa). the execution time, when the osc oscillation frequency is 250khz, is 40 m s. (6) function set 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 0 db 5 1 db 4 s/c db 3 r/l db 2 x db 1 x db 0 instruction code x : don't care 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 1 db 5 8b/4b db 4 n db 3 f db 2 x db 1 x db 0 instruction code x : don't care nf l l h h l h l h number of display lines 1 1 2 2 character font 5x7 dots 5x10 dots 5x7 dots 5x7 dots duty ratio 1/8 1/11 1/16 1/16 number of biases 4 4 5 5 number of common signals 8 11 16 16 the execution time, when the osc oscillation frequency is 250khz, is 40 m s 1 when 8b/4b = "h", the data input/output to and from the cpu is carried out in one step using 8 bits of db 7 to db 0 . when 8b/4b = "l", the data input/output to and from the cpu is carried out in two steps using 4 bits of db 7 to db 4 . 2 the 2-line display mode of the lcd is selected when n = "h", while the 1-line display mode is selected when n = "l". 3 the 5 7 dots character font is slected when f = "l", while the 5 10 dots character font is selected when f = "h" and n = "l". do this initial setting prior to other instructions except the busy flag read after power is applied to the MSM6562B-XX. after that, no initial setting other than setting of 8b/4b value can be done.
? semiconductor MSM6562B-XX 33/50 1 rs 1 0 rs 0 0 r/w 0 db 7 1 db 6 c 5 db 5 c 4 db 4 c 3 db 3 c 2 db 2 c 1 db 1 c 0 db 0 instruction code 1 rs 1 0 rs 0 0 r/w 1 db 7 d 6 db 6 d 5 db 5 d 4 db 4 d 3 db 3 d 2 db 2 d 1 db 1 d 0 db 0 instruction code 1 rs 1 1 rs 0 0 r/w e 7 db 7 e 6 db 6 e 5 db 5 e 4 db 4 e 3 db 3 e 2 db 2 e 1 db 1 e 0 db 0 instruction code (7) cg ram address set the cg ram address is set to a value indicated by c 5 to c 0 (binary). once the cg ram address is set, the cg ram is specified until the dd ram address is set. write/read of the character pattern to and from the cpu begins with the current cg ram address indicated by c 5 to c 0 . the execution time, when the osc oscillation frequency is 250khz, is 40 m s. (8) dd ram address set the dd ram address is set to a value indicated by d 6 to d 0 (binary). once the dd ram address is set, the dd ram is specified until the cg ram address is set. write/read of the character code to and from the cpu begins with the current dd ram address indicated by d 6 to d 0 . in the 1-line mode (n="l"), d 6 to d 0 (binary) must be set to one of the values among "00" to "4f" (hex.). likewise, in the 2-line mode (n="h"), d 6 to d 0 (binary) must be set to one of the values among "00" to "27" (hex.) or "40" to "67" (hex.). when any value other than the above is input, it is impossible to make a normal write/ read of character codes to and from the dd ram. the execution time, when the osc oscillation frequency is 250khz, is 40 m s. e 7 to e 0 (binary) codes are written to the dd ram or cg ram. once they are written, the cursor and display move as described in "(5) cursor/display shift". the execution time, when the osc oscillation frequency is 250khz, is 40 m s. (9) dd ram and cg ram data write
? semiconductor MSM6562B-XX 34/50 (10) busy flag and address counter read (execution time = 1 m s) the busy flag (bf) is output by this instruction to indicate whether the msm6562b is engaged in internal operations (bf = "h") or not (bf = "l"). when bf = "h", no new instruction is accepted. it is therefore necessary to confirm bf = "l" before inputting a new instruction. when bf = "l", a correct address counter value is output. the address counter value must match the dd ram address or cg ram address. the decision of whether it is a dd ram address or cg ram address is made by the address previously set. since the address counter value when bf = "h" may be incremented or decremented by 1 during internal operations, it is not always a correct value. (11) dd ram and cg ram data read character codes (p 7 to p 0 ) are read from the dd ram, and character patterns (p 7 to p 0 ) are read from the cg ram. selection of dd ram or cg ram is decided by the address previously set. after reading those data, the address counter (adc) is incremented or decremented by 1 as set by the shift mode mentioned in item "(3) entry mode setting". the execution time, when the osc oscillation frequency is 250khz, is 40 m s. (note) correct data is read if any of the following conditions are met: 1 when the dd ram address or cg ram address setting instruction is input before inputting this instruction. 2 when the cursor/display shift instruction is input before inputting this instruction in cases where case the character code from the dd ram is read. 3 when reading the data after the second reading from ram when read more than once. correct data is not output in any other case. the execution time, when the osc oscillation frequency is 250khz, is 40 m s. 1 rs 1 0 rs 0 1 r/w bf db 7 o 6 db 6 o 5 db 5 o 4 db 4 o 3 db 3 o 2 db 2 o 1 db 1 o 0 db 0 instruction code 1 rs 1 1 rs 0 1 r/w p 7 db 7 p 6 db 6 p 5 db 5 p 4 db 4 p 3 db 3 p 2 db 2 p 1 db 1 p 0 db 0 instruction code
? semiconductor MSM6562B-XX 35/50 0 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 1 db 5 f 4 db 4 f 3 db 3 f 2 db 2 f 1 db 1 f 0 db 0 instruction code 0 23456789abcdef 1 10 11 12 13 14 15 16 17 18 191a1b1c1d1e 1f v 5 ' pin voltage v 5 ' pin voltage v dd contrast data the voltage between v dd and v 5 ' becomes v lcd . (12) contrast adjusting data write the contrast adjusting data (f 4 to f 0 ) is written to the contrast register. after writing, the voltage output to v 5 ' is changed according to the data. when the contents of the contrast register are "1f" (hex.), the v lcd becomes maximum. when they are "00" (hex.), it becomes minimum. (the contrast adjusting is valid only when the v 5 ' and v 5 pins are connected externally.) the execution time, when the osc oscillation frequency is 250khz, is 40 m s.
? semiconductor MSM6562B-XX 36/50 0 rs 1 0 rs 0 1 r/w 0 db 7 0 db 6 0 db 5 g 4 db 4 g 3 db 3 g 2 db 2 g 1 db 1 g 0 db 0 instruction code (13) contrast adjusting data read the contents (g 4 to g 0 ) of the contrast register are read out. the execution time, when the osc oscillation frequency is 250khz, is 40 m s.
? semiconductor MSM6562B-XX 37/50 14. interface with lcd and the character extension ic (msm5259) display examples when setting the 5 7 dots character font 1-line mode (figure 1), 5 10 dots character font 1-line mode (figure 2), and 5 7 dots character font 2-line mode (figs. 3 and 4) through instructions are shown below. when the 5 7 dots character font is set in the 1-line display mode, com 9 to com 16 output the com signals for turning the display off. likewise, when the 5 10 dots character font is set in the 1-line display mode, com 12 to com 16 output the com signals for turning the display off. the display examples show 20 characters (40 characters in figure 3, 32 characters in figure 4). when the number of msm5259s are increased according to the increase in the number of characters, it is possible to display a maximum of 80 characters. the bias voltage required to operate the lcd is made by a bias dividing resistor built in the MSM6562B-XX and this voltage must be input to the msm5259. these bias examples are shown in figures 5, 6, 7 and 8 and there are following two ways for adjusting the bias voltage. as shown in figures 5 and 6, this method divides the bias by installing vr to v 5 . on the other hand, as shown in figures 7 and 8, this uses the built-in contrast adjusting circuit by connecting v 5 and v 5 '. figure 9 shows the connection of the MSM6562B-XX and the msm5259 including the bias circuit. (the example shows the display of 40 characters and 2 lines using the built-in contrast adjusting circuit.) in addition, the bias voltage must keep the potential relation of v dd > v 1 > v 2 3 v 3 (= v 3 ') > v 4 > v 5 3 v ss . ? in the case of 1-line 20-character display (5 7 dot/font) com 1 com 8 seg 1 seg 100 MSM6562B-XX do cp l df figure 1
? semiconductor MSM6562B-XX 38/50 ? in the case of 1-line 20-character display (5 10 dot/font) ? in the case of 2-line 20 character display (5 7 dot/font) com 1 com 11 seg 1 seg 100 MSM6562B-XX do cp l df figure 2 com 9 com 16 seg 1 seg 100 MSM6562B-XX do cp l df com 1 com 8 figure 3
? semiconductor MSM6562B-XX 39/50 ? in the case of 2-line 16-character display (5 7 dot/font) com 9 com 16 seg 1 seg 80 MSM6562B-XX do cp l df com 1 com 8 seg 100 figure 4
? semiconductor MSM6562B-XX 40/50 ?v lcd variable circuit using external vr (1-line display mode, 1/4 bias) ?v lcd variable circuit using external vr (2-line display mode, 1/5 bias) v 1 v 2 v 3 ' v 3 v 4 v 5 v 5 ' v dd v dd MSM6562B-XX v lcd vr v ss figure 5 v 1 v 2 v 3 ' v 3 v 4 v 5 v 5 ' v dd v dd MSM6562B-XX v lcd figure 6 vr v ss v 1 v 2 v 3 ' v 3 v 4 v 5 v 5 ' v dd v dd MSM6562B-XX v lcd figure 7 v 2 v 3 ' v 3 v 4 v 5 v 5 ' v dd v dd MSM6562B-XX v lcd figure 8 v 1 ? internal v lcd variable circuit (1-line display mode, 1/4 bias) ? internal v lcd variable circuit (2-line display mode, 1/5 bias) (v lcd : lcd driving voltage)
? semiconductor MSM6562B-XX 41/50 ? connection between MSM6562B-XX and msm5259 (40 characters, 2 lines) com 1-16 seg 1-100 do cp l df v dd v ss v 2 v 3 ' v 3 v 4 v 5 v 5 ' v 1 MSM6562B-XX do 40 di 1 cp load df do 20 di 21 o 1 - o 40 v dd v ss v 2 v 3 v ee msm5259 do 40 di 1 cp load df do 20 di 21 o 1 - o 40 v dd v ss v 2 v 3 v ee msm5259 do 40 di 1 cp load df do 20 di 21 o 1 - o 20 v dd v ss v 2 v 3 v ee msm5259 +5v 0v lcd figure 9
? semiconductor MSM6562B-XX 42/50 15. instruction initialization (1) when data input/output to and from the cpu is carried out by 8 bits (db 0 to db 7 ) : 1 ? turn on the power. 2 ? wait for 15ms or more after v dd has reached 4.5v or more. 3 ? set 8b/4b to "h" by the function setting instruction. 4 ? wait for 4.1ms or more. 5 ? set 8b/4b to "h" by the function setting instruction. 6 ? wait for 100 m s or more. 7 ? set 8b/4b to "h" by the function setting instruction. 8 ? check the busy flag as no busy. 9 ? set 8b/4b to "h", the number of lines displayed on lcd (n) and character font (f) by the function setting instruction. (after this, the number of lines displayed on lcd and character font cannot be changed.) 0 ? check no busy. a ? display off by the display on/off control instruction. b ? check no busy. c ? execute the display clear instruction. d ? check no busy. e ? execute the entry mode setting instruction. f ? check no busy. g ? initialization completed. example of instruction code for steps 3 , 5 and 7 . (2) when data input/output to and from the cpu is carried out by 4 bits (db 4 to db 7 ) : 1 ? turn on the power. 2 ? wait for 15ms or more after v dd has reached 4.5v or more. 3 ? set 8b/4b to "h" by the function setting instruction. 4 ? wait for 4.1ms or more. 5 ? set 8b/4b to "h" by the function setting instruction. 6 ? wait for 100 m s or more. 7 ? set 8b/4b to "h" by the function setting instruction. 8 ? check the busy flag as no busy (or wait for 100 m s or more). 9 ? set 8b/4b to "l" by the function setting instruction. 0 ? wait for 100 m s or more. a ? set 8b/4b to "l", the number of lines displayed on lcd (n) and character font (f) by the function setting instruction. (after this, the number of lines displayed on lcd and character font cannot be changed.) 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 1 db 5 1 db 4 x db 3 x db 2 x db 1 x db 0 x : don't care
? semiconductor MSM6562B-XX 43/50 b ? check no busy. c ? display off by the display on/off control instruction. d ? check no busy. e ? execute the display clear instruction. f ? check no busy. g ? execute the entry mode setting instruction. h ? check no busy. i ? initialization completed. example of instruction code for steps 3 , 5 and 7 . 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 1 db 5 1 db 4 1 rs 1 0 rs 0 0 r/w 0 db 7 0 db 6 1 db 5 0 db 4 1 rs 1 0 rs 0 1 r/w bf db 7 o 6 db 6 o 5 db 5 o 4 db 4 example of instruction code for step 8 . example of instruction code for step 9 . execute steps a to h with two-step accesses in 4 bits.
? semiconductor MSM6562B-XX 44/50 16. lcd driving waveforms figures 10, 11 and 12 show the lcd driving waveforms that consist of com waveforms, seg waveform, df (display frequency) signal and l (latch pulse) signal, in the duty of 1/8, 1/11 and 1/16 respectively. the relation between duty and frame frequency is as follows: (note) the osc oscillation frequency is assumed to be 250khz. duty 1/8 1/11 1/16 frame frequency 78.1hz 56.8hz 78.1hz
? semiconductor MSM6562B-XX 45/50 figure 10 lcd driving waveforms at 1/8 duty 7812345678123456781 2 v dd v 1 v 2 ,v 3 v 4 v 5 com 1 v dd v 1 v 2 ,v 3 v 4 v 5 com 2 v dd v 1 v 2 ,v 3 v 4 v 5 com 8 v dd v 1 v 2 ,v 3 v 4 v 5 com 9 v dd v 1 v 2 ,v 3 v 4 v 5 seg v dd v 1 v 2 ,v 3 v 4 v 5 com 16 1 frame df l display turning-off waveform display turning-on waveform (output example)
? semiconductor MSM6562B-XX 46/50 figure 11 lcd driving waveforms at 1/11 duty 1011123456789101112345 v dd v 1 v 2 ,v 3 v 4 v 5 com 1 v dd v 1 v 2 ,v 3 v 4 v 5 com 2 v dd v 1 v 2 ,v 3 v 4 v 5 com 11 v dd v 1 v 2 ,v 3 v 4 v 5 com 12 v dd v 1 v 2 ,v 3 v 4 v 5 seg v dd v 1 v 2 ,v 3 v 4 v 5 com 16 1 frame df l display turning-off waveform display turning-on waveform (output example)
? semiconductor MSM6562B-XX 47/50 figure 12 lcd driving waveforms at 1/16 duty 151612345678910111213141516 v dd v 1 v 2 v 3 v 4 com 1 v dd v 1 v 2 v 3 v 4 com 2 v dd v 1 v 2 v 3 v 4 seg v dd v 1 v 2 v 3 v 4 com 16 1 frame df l display turning-off waveform v 5 v 5 v 5 v 5 1 2 3 4 display turning-on waveform (output example)
? semiconductor MSM6562B-XX 48/50 pad configuration pad layout chip size : 7.12 4.09 mm pad size : 100 100 m m (pv hole) 210 100 m m (v dd , v ss ) chip thickness : 525 20 m m pad coordinates note : the chip substrate should be connected to v dd or left open. 1t 2 C3275 C1900 pad symbol x (m) y (m) pad symbol x (m) y (m) 2t 3 C3135 C1900 3v ss C2940 C1900 4 com1 C2745 C1900 5 com2 C2605 6 com3 C2465 7 com4 C2325 8 com5 C2185 9 com6 C2045 10 com7 C1905 com8 com9 11 12 13 14 15 16 17 18 19 com10 com11 com12 com13 com14 com15 com16 C1765 C1625 C1485 C1345 C1205 C1065 C925 C785 C645 21 seg99 C365 C1900 22 seg98 C225 23 seg97 C85 24 seg96 55 25 seg95 195 26 seg94 335 27 seg93 475 28 seg92 615 29 seg91 755 30 31 32 33 34 35 36 37 38 39 seg90 seg89 seg88 seg87 seg86 seg85 seg84 seg83 seg82 seg81 895 1035 1175 1315 1455 1595 1735 1875 2015 2155 20 seg100 C505 40 seg80 2295 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 C1900 x y 122 123 149 1 76 75 48 47
? semiconductor MSM6562B-XX 49/50 pad symbol x (m) y (m) symbol x (m) y (m) pad 41 seg79 2435 C1900 42 seg78 2527 C1900 43 seg77 2715 C1900 44 seg76 2855 C1900 45 seg75 2995 C1900 46 seg74 3135 C1900 47 seg73 3275 C1900 48 seg72 3415 C1900 49 seg71 C1750 50 51 52 53 54 55 56 57 58 59 seg70 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 C1610 C1470 C1330 C1190 C1050 C910 C770 C630 C490 C350 C210 C70 60 61 62 63 64 65 66 67 68 69 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 70 210 350 490 630 770 910 1050 70 71 72 73 74 75 76 77 78 79 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 1190 1330 1470 1610 1750 1900 3275 3135 2995 2855 2715 2575 2435 2295 2155 80 seg40 81 seg39 82 seg38 83 seg37 84 seg36 86 seg34 1875 1900 87 seg33 1735 88 seg32 1595 89 seg31 1455 90 seg30 1315 91 seg29 1175 92 seg28 1035 93 seg27 895 94 seg26 755 95 96 97 98 99 100 101 102 103 104 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 615 475 335 195 55 C85 C225 C365 C505 C645 C785 C925 C1065 C1205 105 106 107 108 109 110 111 112 113 114 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 C1345 C1485 C1625 C1765 C1905 C2045 115 116 117 118 119 120 121 122 123 124 seg5 seg4 seg3 seg2 seg1 v dd shl0 shl1 osc1 oscr C2185 osc2 C2325 C2465 C2605 C2745 C2940 C3135 C3275 C3415 1820 1680 1540 1400 1260 1120 980 C3415 C3415 C3415 C3415 C3415 C3415 125 v 1 126 v 2 127 v 3 ' 128 v 3 129 2015 85 seg35 840 C3415 v 4 130 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 pad coordinates (continued)
? semiconductor MSM6562B-XX 50/50 pad symbol x (m) y (m) symbol x (m) y (m) pad 131 v 5 700 132 v 5 ' 560 133 l 420 134 cp 280 135 df 140 136 do 0 137 rs0 C140 138 rs1 C280 139 r/w C420 140 141 142 143 144 145 146 147 148 149 e db0 db1 db2 db3 db4 db5 db6 db7 t 1 C560 C700 C840 C980 C1120 C1260 C1400 C1540 C1680 C1820 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 C3415 pad coordinates (continued)

▲Up To Search▲

Price & Availability of MSM6562B-XX

	To Download MSM6562B-XX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .